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A Modern Approach to Refclk Jitter Analysis for SerDes Applications
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Examines clock-edge variation and phase noise, with attention to jitter budgets, measurement bandwidths and error sources.
Jitter and PLLs
Compare jitter and phase noise under matching bandwidths and operating conditions. PLL bandwidth affects reference and local-oscillator noise transfer and must be evaluated against the system budget.
These are original SIMACITY reading notes, not a verbatim reproduction of the manufacturer article.
Prepared from public SiTime information with original overviews and reading notes. Consult the local manufacturer PDFs for device conditions.